Synopsys is hiring for Intern (Technical-Engineering) | Bachelor’s degree in Electronics/ Electrical Engineering/ MS/MTech | Apply now
Hello Friends!
Today we tell you about a very good opportunity from
Synopsys that is hiring for Intern (Technical-Engineering). Bachelor’s degree in Electronics/ Electrical Engineering and be in their final semester by Jan’22. Or going through MS/MTech and completed first semester and take up internship as part of the 1 year academic project requirement can apply. Kindly go through the full blog post for test pattern , selection process ,CTC, last date to apply and all others the details regarding this opportunity.
We Don't Run Ads. Share now with your friends and batchmates
Want to get more such updates Click here
Want to get more such updates Click here
You all are our promoters just Share with your friends & juniors
Job Description and Requirements
Synopsys is looking for engineering graduates/PG students to work as interns in the field of VLSI.
Description:
The focus of work would be VLSI design/Verification in one of the following areas related to connectivity protocols: USB/Ethernet/AMBA/MIPI/Memory Controllers
The nature of work would be on the following lines:
Architecture exploration of the sub-blocks within one of these IPs to optimize for area, speed and power
VLSI Design & verification of these sub-blocks/exploration of latest features and standards.
Based on project assigned, the job would involve one or more of the following activities: Verilog/System Verilog/ Vera coding, Exposure to UVM methodology, working with EDA tools like Design Compiler for Synthesis, SpyGlass for Lint, VCS for simulation.
Requirements:
The candidate must be doing their Bachelor’s degree in Electronics/ Electrical Engineering and be in their final semester by Jan’22.
Or going through MS/MTech and completed first semester and take up internship as part of the 1 year academic project requirement . (Electrical/Electronics/VLSI/MicroElectronics or allied specializations.)
Minimum 7.0 CGPA/ 70% in Bachelor’s in Engineering and 7.5 CGPA in Master’s till the current semester.
Need to be backed with consistently high academics in 10th std and 12th standard.
Strong fundamentals in Digital electronics.
HDL Languages coding experience preferably in Verilog/Vera/System Verilog.
Tenure: Typically, 12 months.
Location: The positions are based out of Synopsys offices at Bangalore and would require the candidate to physically work out of Synopsys offices during the office hours 5 days/ week during the internship tenure.
Note: Synopsys converts many of its Interns to full time employees after the completion of internship and based on performance during the internship tenure and business needs.
Job Description and Requirements
Synopsys is looking for engineering graduates/PG students to work as interns in the field of VLSI.
Description:
The focus of work would be VLSI design/Verification in one of the following areas related to connectivity protocols: USB/Ethernet/AMBA/MIPI/Memory Controllers
The nature of work would be on the following lines:
Architecture exploration of the sub-blocks within one of these IPs to optimize for area, speed and power
VLSI Design & verification of these sub-blocks/exploration of latest features and standards.
Based on project assigned, the job would involve one or more of the following activities: Verilog/System Verilog/ Vera coding, Exposure to UVM methodology, working with EDA tools like Design Compiler for Synthesis, SpyGlass for Lint, VCS for simulation.
Requirements:
The candidate must be doing their Bachelor’s degree in Electronics/ Electrical Engineering and be in their final semester by Jan’22.
Or going through MS/MTech and completed first semester and take up internship as part of the 1 year academic project requirement . (Electrical/Electronics/VLSI/MicroElectronics or allied specializations.)
Minimum 7.0 CGPA/ 70% in Bachelor’s in Engineering and 7.5 CGPA in Master’s till the current semester.
Need to be backed with consistently high academics in 10th std and 12th standard.
Strong fundamentals in Digital electronics.
HDL Languages coding experience preferably in Verilog/Vera/System Verilog.
Tenure: Typically, 12 months.
Location: The positions are based out of Synopsys offices at Bangalore and would require the candidate to physically work out of Synopsys offices during the office hours 5 days/ week during the internship tenure.
Note: Synopsys converts many of its Interns to full time employees after the completion of internship and based on performance during the internship tenure and business needs.
How to Apply for Synopsys drive:
How to Apply for Synopsys drive:
If you went through all the details of the job and you are eligible then you can apply via clicking on apply now.
Find more recent drives Click here
Find more recent drives Click here
Important Note While Applying for Jobs:- Do read all the instructions and requirements carefully before applying for the job. All the communications from the organization will be on your registered Email ID. Keep checking your mailbox for the next round of details once candidature is shortlisted.
Disclaimer:- FRESHERS HIRING JOBS platform is a free Job Sharing platform for all Job seekers. We don’t charge any cost and service fee for any job which is posted on our website, neither we have authorized anyone to do the same. Most of the jobs posted over FRESHERS HIRING JOBS are taken from the career pages of the organizations. CTC amount is either provided by the company or mentions on online platforms like glassdoor, ambition box, etc hence its possibility of variation in your salary. Jobseekers/Applicants are advised to check all the details when they apply for the job to avoid any inconvenience.
Join our Social Media Handle for quick notifications:This Job may not matter to you but it matters most for someone in your contact So, Keep Sharing..... with the needy one.
Find more recent drives Click here
Find more recent drives Click here
Comments
Post a Comment